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oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation solved by tm sp6138 features 5v to 24v input step down converter up to 3a output in a small form factor highly integrated design, minimal components uvlo detects both v cc and v in overcurrent circuit protection with auto-restart power good output, enable input maximum controllable duty cycle ratio up to 92% wide bw amp allows type ii or iii compensation programmable soft start fast transient response available in 6-pin qfn package external driver enable/disable u.s. patent #6,922,04 synchronous buck controller the sp6 38 is a synchronous step-down switching regulator controller optimized for small footprint. the part is designed to be especially attractive for single supply step down con - version from 5v to 24v. the sp6 38 is designed to drive a pair of external nfets using a fxed 2.5 mhz frequency, pwm voltage mode architecture. protection features include uvlo, thermal shutdown, output short circuit protection, and overcurrent protection with auto restart. the device also features a pwrgd output and an enable input. the sp6 38 is available in a space saving 6-pin qfn and offers excellent thermal performance. typical application circuit now available in lead free packaging description rs3 4.99k? cbst 0.1uf r1 68.1k?, 1% rz3 1k? r2 21.5k?, 1% mt/mb, si7214dn 47 m?, 30v cz3 47pf (co-packaged fets) cp1 6 pf rz2 54.9k? cz2 100pf cf1 18pf 12v csp 6.8nf vin gnd vout gnd ss vcc powergood css 47nf isp isn en pgnd gnd pwrgd vfb comp vin bst gh swn uvin gl 3.3v 0-2a dbst sd101aws cvcc 4.7uf c5 0.1uf r3 10k? sp6138 c1 4.7uf nc cs 0.1uf rs2 1k? rs1 1k? cooper, sd25-2r2 2.2uh, 2.8a, 31m? c2 22uf enable note: die-attach paddle is connected to gnd isn ss en co mp sp613 8 16 pin qf n 3mm x 3m m v in 8 7 6 5 4 3 2 1 gh bst uv in gl pgn d v fb 12 11 10 9 16 15 14 13 gn d pwrg d isp sw n v cc
2 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation parameter min typ max units conditions quiescent current v in supply current .5 3.0 ma vfb = v (no switching) vcc supply current .5 3.0 ma vfb = v (no switching) bst supply current 0.2 0.4 ma vfb = v (no switching) protection: uvlo vcc uvlo start thresh - old 4.00 4.25 4.5 v vcc uvlo hysteresis 50 200 250 mv uv in start threshold 2.35 2.50 2.65 v apply voltage to uv in pin uv in hysteresis 200 300 400 mv apply voltage to uv in pin v in start threshold 9.0 9.5 0.0 v uv in floating v in hysteresis 300 mv uv in floating enable pullup current 0.4 a apply voltage to en pin error amplifier reference error amplifer reference 0.792 0.800 0.808 v 2x gain confg. error amplifer reference over line and temperature 0.788 0.800 0.82 v comp sink current 70 50 230 a comp source current -230 -50 -70 a vfb input bias current 50 00 na comp common mode output range .9 3.0 3.2 v comp pin clamp voltage 3.2 3.5 3.8 v vfb = 0.7v electrical specifications unless otherwise specifed: -40c < t amb < 85c, 4.5v < v cc < 5.5v, bst=v cc , swn = gnd = pgnd = 0.0v, uv in = 3.0v, cv cc = 0f, c comp = 0. f, cgh = cgl = 3.3nf, c ss = 50nf, r pwrgd = 0k . these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifcations below is not implied. exposure to absolute maxi - mum rating conditions for extended periods of time may affect reliability. v cc .................................................................................................. 6v v in .............................................................................................. 24.5v bst ................................................................................................ 30v bst-swn ........................................................................................ 7v swn .................................................................................... -2v to 24v gh .......................................................................... -0.3v to bst+0.3v gh-swn .......................................................................................... 6v all other pins ............................................................ -0.3v to v cc +0.3v peak output current < 10s gh,gl ............................................................................................. 2a storage temperature ................................................... -65c to 150c power dissipation ........................................................................... w esd rating ........................................................................... 2kv hbm thermal resistance .............................................................. 41.9c/w absolute maximum ratings
3 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation electrical specifications unless otherwise specifed: -40c < t amb < +85c, 4.5v < v cc < 5.5v, bst=v cc ,swn = gnd = pgnd = 0.0v, uv in = 3.0v, cv cc = 0. f, c comp = 0. f, cgh = cgl = 3.3nf, c ss = 50nf. parameter min typ max units conditions control loop: pwm comparator, ramp & loop delay path ramp offset .7 2.0 2.3 v t a = 25?c ramp amplitude 0.80 .0 .20 v gh minimum pulse width 30 70 ns maximum controllable duty ratio 92 % maximum duty ratio 00 % guaranteed by design internal oscillator frequency 2.2 2.5 2.8 mhz timers: softstart ss charge current -6 -0 -4 a ss discharge current .0 2.0 3.0 ma fault present vcc linear r egulator vcc output voltage 4.6 5.0 5.4 v vin = 6 to 23v, iload = 0ma to 30ma dropout voltage 250 500 750 mv ivcc = 30ma power good output power good threshold -0 -7.5 -5 % power good hysteresis 2.0 4.0 % power good sink current .0 0 ma v fb = 0.7v, v pwrgd = 0.2v protection: short circuit & thermal short circuit threshold voltage 0.2 0.25 0.3 v measured v ref (0.8v) - v fb overcurrent threshold voltage 54 60 66 mv measured isp - isn isp, isn common mode range 0 3.3 v hiccup timeout 20 30 40 ms thermal shutdown temperature 35 45 55 ?c thermal hysteresis 0 3.3 ?c
4 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation electrical specifications unless otherwise specifed: -40c < t amb < +85c, 4.5v < v cc < 5.5v, bst=v cc ,swn = pgnd = gnd = 0.0v, u vin = 3.0v, cv cc = 0. f, c comp = 0. f, cgh = cgl = 3.3nf, c ss = 50nf. parameter min typ max units conditions output: nfet gate drivers gh & gl rise times 35 50 ns m easured 0% to 9 0% gh & gl fall times 30 40 ns m easured 90% to 0% gl to gh non overlap time 45 70 ns gh & gl measured at 2.0v swn to gl non overlap time 25 40 ns measured swn = 00mv to gl = 2.0v gh & gl pull down re - sistance 5 50 85 k? driver pull down resistance .5 .9 ? driver pull up resistance 2.5 3.9 ? block diagram 2 . 5 m h z n o n s y n c . s t a r t u p 1 0 0 m s d e l a y f a u l t 0 . 1 v 0 . 2 5 v s o f t s t a r t i n p u t 1 3 5 o c o f f 1 4 5 o c o n 5 0 k? 1 4 0 k? 1 . 0 v o f f 1 . 7 v o n 4 . 0 5 v o f f 4 . 2 5 v o n f a u l t r f a u l t 6 e n 1 u a v c c v c c 3 g n d e n a b l e c o m p a r a t o r c o m p a r a t o r 1 . 6 v s s g l h o l d o f f c l k c l o c k p u l s e g e n e r a t o r q s r e s e t d o m i n a n t q p w m s y n c h r o n o u s d r i v e r 1 3 1 2 1 1 1 2 p g n d b s t 7 9 1 0 1 5 1 4 1 6 8 5 2 . 8 v 1 . 3 v r a m p = 1 v v f b p o w e r g o o d p w r g d 0 . 7 2 v o f f 0 . 7 4 v o n v p o s t h e r m a l a n d o v e r c u r r e n t p r o t e c t i o n u v l o c o m p a r a t o r s v c c u v l o h i c c u p f a u l t r e f o k c o u n t e r c l r c l k i s p i s n 6 0 m v o v e r c u r r e n t d e t e c t i o n d e t e c t i o n v f b i n t s h o r t c i r c u i t q d o m i n a n t r s s e t s h u t d o w n t h e r m a l v i n r e f o k c o r e 0 . 8 v u v i n v i n u v l o 2 . 5 0 v o n 2 . 2 0 v o f f r e g u l a t o r l i n e a r 5 v r e f e r e n c e p o w e r f a u l t v c c p o s r e f f a u l t v c c s s 1 0 u a v c c v f b i n t 4 v f b g l p w m l o o p c o m p v p o s g m g m e r r o r a m p l i f i e r g h s w n
5 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation pin description theory of operation general overview the sp6138 is a fxed frequency, voltage mode, synchronous pwm controller opti - mized for high effciency. the part has been designed to be especially attractive for single supply input voltages ranging between 5v and 24v. the heart of the sp6 38 is a wide bandwidth transconductance amplifer designed to ac - commodate type ii and type iii compensa - tion schemes. a precision 0.8v reference present on the positive terminal of the error amplifer permits the programming of the output voltage down to 0.8v via the v fb pin. the output of the error amplifer, comp, compared to a v peak-to-peak ramp is responsible for trailing edge pwm control. this voltage ramp and pwm control logic are governed by the internal oscillator that ac - curately sets the pwm frequency to 2.5 mhz. pin # pin name description gl high current driver output for the low side nfet switch. it is always low if gh is high or during a fault. resistor pull down ensures low state at low voltage. 2 pgnd ground pin. the power circuitry is referenced to this pin. return separately from other ground traces to the (-) terminal of cout. 3 gnd ground pin. the control circuitry of the ic is referenced to this pin. 4 vfb feedback voltage and short circuit detection pin. it is the inverting input of the error amplifer and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. whenever vfb drops 0.25v below the positive reference, a short circuit fault is detected and the ic enters hiccup mode. 5 comp output of the error amplifer. it is internally connected to the non-inverting input of the pwm comparator. an optimal flter combination is chosen and connected to this pin and either ground or vfb to stabilize the voltage mode loop. 6 en enable pin. pulling this pin below 0.4v will place the ic into sleep mode. this pin is internally pulled to vcc with a a current source. 7 pwrgd power good output. this open drain output is pulled low when vout is outside of the regulation. connect an external resistor to pull high. 8 ss soft start/fault flag. connect an external capacitor between ss and gnd to set the soft start rate based on the 0a source current. the ss pin is held low via a ma (min) current during all fault conditions. 9 isn negative input for the sense comparator. there should be a 60mv offset between psense and nsense. offset accuracy + 0%. 0 isp positive input for the inductor current sense. swn lower supply rail for the gh high-side gate driver. connect this pin to the switching node at the junction between the two external power mosfet transistors. 2 gh h igh current driver output for the high side nfet switch. it is always low if gl is high or during a fault. 3 bst high side driver supply pin. connect bst to the external boost diode and capacitor as shown i n the application schematic of page . high side driver is connected between bst pin and swn pin. 4 vin s upply input. provides power to the internal ldo. 5 uvin under voltage lock-out for vin voltage. internally has a resistor divider from vin to ground. can be overridden with external resistors. 6 vcc output of the internal ldo. if vin is less than 5v then vcc should be powered from an external 5v supply. note: die-attach paddle is internally connected to gnd
6 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation theory of operation the sp6138 contains two unique control features that are very powerful in distributed applications. first, non-synchronous driver control is enabled during start up to prohibit the low side nfet from pulling down the out - put until the high side nfet has attempted to turn on. second, a 00% duty cycle timeout ensures that the low side nfet is periodically enhanced during extended periods at 00% duty cycle. this guarantees the synchronized refreshing of the bst capacitor during very large duty ratios. the sp6 38 also contains a number of valu - able protection features. a programmable input uvlo allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal v cc uvlo ensures that the controller itself has enough voltage to properly operate. other protection features include thermal shutdown and short-circuit detection. in the event that either a thermal, short-circuit, or uvlo fault is de - tected, the sp6 38 is forced into an idle state where the output drivers are held off for a fnite period before a re-start is attempted. soft start soft start is achieved when a power con - verter ramps up the output voltage while controlling the magnitude of the input sup - ply source current. in a modern step down converter, ramping up the non-inverting input of the error amplifer controls soft start. as a result, excess source current can be defned as the current required to charge the output capacitor iv in, x = c out ? ?v out ?tsoft-start the sp6 38 provides the user with the op - tion to program the soft start rate by tying a capacitor from the ss pin to gnd. the selection of this capacitor is based on the 0a pull up current present at the ss pin and the 0.8v reference voltage. therefore, the excess current source can be redefned as: iv in, x = c out ? ?v out ? 0a (c ss ? 0.8v) hiccup upon the detection of a power, thermal, or short-circuit fault, the sp6 38 is forced into an idle state for a minimum of 30ms. the ss and comp pins are immediately pulled low, and the gate drivers are held off for the dura - tion of the timeout period. power and thermal faults have to be removed before a restart may be attempted, whereas, a short-circuit fault is internally cleared shortly after the fault latch is set. therefore, a restart attempt is guaranteed every 30ms (typical) as long as the short-circuit condition persists. a short-circuit detection comparator has also been included in the sp6 38 to protect against the accidental short or severe build up of current at the output of the power con - verter. this comparator constantly monitors the inputs to theerror amplifer, and if the v fb pin ever falls more than 250mv (typical) below the reference voltage, a short-circuit fault is set. because the ss pin overrides the internal 0.8v reference during soft start, the sp6 38 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. error amplifer & voltage loop as stated before, the heart of the sp6 38 voltage error loop is a high performance, wide bandwidth transconductance ampli - fer. because of the amplifers current limited ( + 00a) transconductance, there are many ways to compensate the voltage loop or to control the comp pin externally. if a simple, single pole, single zero response is required, then compensation can be as simple as an rc circuit to ground. if a more complex compensation is required, then the amplifer has enough bandwidthto run type iii compensation schemes with adequate gain and phase margins at crossover frequencies greater than 200 khz.
7 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation theory of operation the common mode output of the error ampli - fer (comp) is 0.9v to 2.2v. therefore, the pwm voltage ramp has been set between .0v and 2.0v to ensure proper 0% to 00% duty cycle capability. the voltage loop also includes two other very important features. one is an non-synchronous start up mode. basically, the gl driver cannot turn on unless the gh driver has attempted to turn on or the ss pin has exceeded .7v. this feature prevents the controller from dragging down the output voltage during startup or in fault modes. the second feature is a 00% duty cycle timeout that ensures synchronized refreshing of the bst capacitor at very high duty ratios. in the event that the gh driver is on for 20 continuous clock cycles, a reset is given to the pwm fip fop half way through the 20th cycle. this forces gl to rise for the remainder of the cycle, in turn refreshing the bst capacitor. gate drivers the sp6 38 contains a pair of powerful 2.5 ? pull-up and .5 ? pull-down drivers. these state-of-the-art drivers are designed to drive an external nfet capable of handling up to 30a. rise, fall, and non-overlap times have all been minimized to achieve maximum effciency. all drive pins gh, gl, & swn are monitored continuously to ensure that only one external nfet is ever on at any given time. thermal & short-circuit protection because the sp6 38 is designed to drive large nfets running at high current, there is a chance that either the controller or power converter will become too hot. therefore, an internal thermal shutdown (145c) has been included to prevent the ic from malfunction - ing at extreme temperatures. over-current protection over-current is detected by monitoring a differential voltage across the output induc - tor as shown in fgure 1. inputs to an over- current detection comparator, set to trigger at 60 mv nominal, are connected to the in - ductor as shown. since the average voltage sensed by the comparator is equal to the product of in - ductor current and inductor dc resistance (dcr) then i max = 60mv / dcr. solving this equation for the specifc inductor in cir - cuit , i max = 4.6a. when i max is reached, a 220 ms time-out is initiated, during which top and bottom drivers are turned off. fol - lowing the time-out, a restart is attempted. if the fault condition persists, then the time- out is repeated (referred to as hiccup). figure 1: over-current detection circuit is n sp 613x sw n is p v out l = 2. 7uh , dcr = 4 . mo hm rs 5. k rs 2 5. k cs 0. uf cs p 6. 8n f
8 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation application information increasing the current l imi t if it is desired to set imax > { 60mv / dcr } (in this case larger than 4.6a), then a resis - tor r s3 should be added as shown in fgure 2. r s3 forms a resistor divider and reduces the voltage seen by the comparator. since: 60mv ( i max ? dcr ) r s3 = { r s + r s2 + r s3 } solving for rs3 we get: r s3 = [60mv ? (r s + r s2 )] .........(2a) [ (imax ? dcr) C 60mv ] as an example: if desired i max is 7a, then r s3 = 63.4k ? . figure 2- over-current detection circuit for imax > 60mv / dcr decreasing the current l imi t if it is required to set imax < { 60mv / dcr } , a resistor is added as shown in fgure 3. rs3 increases the net voltage detected by the current-sense comparator. voltage at the positive and negative terminal of compara - tor is given by: vsp = v out + (i max ? dcr) vsn = v out x {r s3 / (r s2 +r s3 )} since the comparator is triggered at 60mv: vsp-vsn = 60 mv combining the above equations and solv - ing for r s3 : r s3 = r s2 ? [ v out - 60mv + (i max ? dcr) ] .........(2b) 60mv - (i max ? dcr) as an example: for i max of 2a and v out of 3.3v, calculated r s3 is .5m (232k standard). figure 3- over-current detection circuit for i max < {60mv / dcr} power mosfet selection there are four main criterion in selecting power mosfets for buck conversion: i voltage rating bv dss l on resistance r ds ( on ) l gate-to-drain charge q gd l package type in order to better illustrate the mosfet se - lection process, the following buck converter design example will be used: v in = 2v, v out = 3.3v, i out = 0a, f = 2000khz, dcr = 4.5m ? (inductor dc resistance), effciency = 94% and t a = 40?c. select the voltage rating based on maximum input voltage of the converter. a commonly used practice is to specify bv dss at least twice the maximum converter input voltage. this is done to safeguard against switching transients that may break down the mosfet. for converters with v in of less than 0v, a rs 3 63 .4 k cs p 6. 8n f sw n is p is n sp 613x cs 0. u f rs 2 5. k rs 5. k l = 2. 7uh , dcr = 4. m oh m vo ut cs p 6. 8nf is n sp 613x sw n is p cs 0. uf rs 2 5. k rs 5. k vo ut l = 2. 7uh , dcr = 4. m oh m rs 3 . 5m oh m
9 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation 20v rated mosfet is suffcient. for convert - ers with 0-5v in , as in the above example, select a 30v mosfet. the calculation of r ds ( on ) for top and bottom mosfets is interrelated and can be done using the following procedure: ) calculate the maximum permissible power dissipation p ( dissipation ) based on required effciency. the converter in the above example should deliver an output power p out = 3.3vx 0a = 33w. for a target effciency of 94%, input power p in is given by p in = p out /0.94 = 35. w. maximum al - lowable power dissipation is then: p ( dissipation ) = p in C p out = 2. w 2) calculate the total power dissipation in top and bottom mosfets p ( mos fe t ) by subtracting inductor losses from p ( dissipation ) calculated in step . to simplify, disregard core losses; then p l = i 2 rms x dcr x .4, where .4 accounts for the increase in dcr at operating temperature. for the above example p l = 0.63w. then: p ( mosfet ) = 2.w C 0.63w = .47w. 3) calculate r ds ( on ) of the bottom mosfet by allocating 40% of calculated losses to it. 40% dissipation allocation refects the fact that the the top mosfet has essentially no switching loss. then p ( bottom ) = 0.4x .47w = 0.59w. r ds ( on ) = p/(i 2 rms x .5) where i rms = i out x { -(v out /v in ) } 0.5 and .5 accounts for the increase in r ds ( on ) at the operating temperature. then: r ds ( on ) = p [ { i 2 out ? (-v out /v in ) } ? .5 ] = 5.4 m ? . 4) allocate 60% of the calculated losses to the top mosfet, p ( top ) = 0.6x .47 = 0.88w. assume conduction losses equal to switching losses, then p = 0.5x0.88w = 0.44w. since it operates at the duty cycle of d=v in /v out ; then: r ds ( on ) = p [ i 2 out ? (v out /v in ) ? .5 ] = 0.7 m ? . gate-to-drain charge q gd for the top mos - fet needs to be specifed. a simplifed expression for switching losses is: ps = i out ? v in ? f ? { v in + i out } ...................(3) d v/dt d i/dt where dv/dt and di/dt are the rates at which voltage and current transition across the top mosfet respectively, and f is the switching frequency. voltage switching time ( v in / d v/dt ) is related to q gd : ( v in / d v/dt ) = q gd / i g ............................... (4) where i g is current charging the gate-to- drain capacitance. it can be calculated from: i g = (v drive -v gat e )/r drive ......................(5) where v drive is the drive voltage of the sp6 38 top driver minus the drop across the boost diode (approximately 4.5v); v gat e is the top mosfets gate voltage correspond - ing to i out (assume 2.5v) and r drive is the internal resistance of the sp6 38 top driver (assume 2 ? average for turn-on and turn-off). substituting these values in equation (5) we get i g = a. substituting for i g in equation (4), we get ( v in / d v/dt ) = q gd . substituting for ( v in / d v/dt ) in equation (3) we have: ps = i out ? v in ? f ? { q gd + (i out / d i/dt ) } solving for q gd we get: q gd = { ps _ i out } .............. (6) i out ? v in ? f d i/dt di/dt is usually limited by parasitic dc-loop inductance (lp) according to di/dt = v in /lp. application information
0 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation lp is due to wiring and pcb traces connecting input capacitors and switching mosfets. for typical lp of 2nh and v in of 2v, di/dt is 1a/ns. substituting for di/dt in equation (6) we get q gd = 2 nc. in selecting a package type, the main con - siderations are cost, power/current handling capability and space constraints. a larger package in general offers higher power and current handling at increased cost. package selection can be narrowed down by calculat - ing the required junction-to-ambient thermal resistance ja : ja = {t j ( max ) - t a ( max ) } / p ( max ) ........... (7) where: t j ( max ) is the die maximum tem - perature rating, t a ( max ) is maximum ambient temperature, and p ( max ) is maximum power dissipated in the die. it is common practice to add a guard-band of 25?c to the junction temperature rating. following this convention, a 150?c rated mosfet will be designed to operate at 125?c (i.e., t j ( max ) = 125?c). p ( max ) = 0.88w (from section 4) and t a ( max ) = 40?c as specifed in the design example. substituting in equation (7) we get ja = 96.6 ?c/w. for the top mosfet, we now have deter - mined the following requirements; bv dss = 30v, r ds ( on ) = 0.7m ? , q gd = 2 nc and ja < 96.6?c/w. an so-8 mosfet that meets the requirements is vishay-siliconixs si4394dy; bv dss = 30v, r ds ( on ) = 9.75m ? @ v gs = 4.5v, q gd = 2.nc and ja = 90 ?c/w. the bottom mosfet has the requirements of bv dss = 30v and r ds ( on ) = 5.4m ? . vishay- siliconixs si4320dy meets the requirements; bvdss = 30v, r ds ( on ) = 4m ? @ vgs = 4.5v. power good power good (pwrgd) is an open drain output that is pulled low when v out is out - side regulation. the pwrgd pin can be connected to vcc with an external 0k ? resistor. during startup, output regulates when soft start (ss) reaches 0.8v (the refer - ence voltage). pwrgd is enabled when ss reaches .6v. pwrgd output can be used as a power on reset. the simplest way to adjust delay of the power on reset signal with respect to v out in regulation is with the soft start capacitor (c ss ) and is given by: c ss = (iss x tdelay)/0.8 where iss is the soft start charge current ( 0a nominal). under voltage lock out (uvlo) the sp6 38 has two separate uvlo com - parators to monitor the bias (vcc) and input (v in ) voltages independently. the vcc uvlo is internally set to 4.25v. the v in uvlo is programmable through uv in pin. when uvin pin is greater than 2.5v the sp6 38 is permitted to start up pending the removal of all other faults. a pair of internal resistors is connected to uvin as shown in fgure 4. therefore without external biasing the v in start threshold is 9.5v. a small capacitor may be required between uvin and gnd to flter out noise. for applications with v in of 5v or 3.3v, connect uvin directly to v in . figure 4- internal and external bias of uvin sp 613x r4 r5 + - 40 k 50k 2. 5v o n 2. 2v o ff gn d uv in vi n application information
oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation to program the v in start threshold, use a pair of external resistors as shown. if external resistors are an order of magnitude smaller than internal resistors, then the v in start threshold is given by: v in ( start ) = 2.5 ? (r4+r5)/r5................ (8) for example, if it is required to have a v in start threshold of 7v, then let r5 = 5k ? and using equation (9) we get r4 = 9.09k ? . inductor selection there are many factors to consider in select - ing the inductor including cost, effciency, size and emi. in a typical sp6 38 circuit, the inductor is chosen primarily for value, saturation current and dc resistance. in - creasing the inductor value will decrease output voltage ripple, but degrade transient response. low inductor values provide the smallest size, but cause large ripple cur - rents, poor effciency and need more output capacitance to smooth out the larger ripple current. the inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. a good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. the switching frequency and the inductor operating point determine the inductor value as follows: l = v out ? ( v in ( max ) - v out ) v in ( max ) ? fs ? k r ? i out ( max ) where: fs = switching frequency k r = ratio of the ac inductor ripple current to the maximum output current the peak to peak inductor ripple current is: i pp = v out ? (v in ( max ) - v out ) v in ( max ) ? f s ? l once the required inductor value is selected, the proper selection of core material is based on peak inductor current and effciency re - quirements. the core must be large enough not to saturate at the peak inductor current i peak = i out ( max ) + i pp / 2 and provide low core loss at the high switch - ing frequency. low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. in general, ferrite or molypermalloy materials are the better choice for all but the most cost sensi - tive applications. the power dissipated in the inductor is equal to the sum of the core and copper losses. to minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. core losses have a more signifcant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output cur - rents where the copper losses dominate. core loss information is usually available from the magnetic vendor. the copper loss in the inductor can be cal - culated using the following equation: p l ( c u ) = i 2 l ( rms ) ? r winding application information
2 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation where i l(rms) is the rms inductor current that can be calculated as follows: i l( rms ) = . . i out ( max ) ? + ? { i pp } 2 3 i out ( max ) output capacitor selection the required esr (equivalent series re - sistance) and capacitance drive the selec - tion of the type and quantity of the output capacitors. the esr must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. during an output load transient, the output capacitor must supply all the ad - ditional current demanded by the load until the sp6 38 adjusts the inductor current to the new value. therefore, the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. additionally, the esr in the output capacitor causes a step in the output volt - age equal to the current. because of the fast transient response and inherent 00% and 0% duty cycle capability provided by the sp6 38 when exposed to output load transients, the output capacitor is typically chosen for esr, not for capacitance value. the output capacitors esr, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. the maximum allowable esr required to maintain a specifed output voltage ripple can be calculated by: r esr < ? v out i pk - pk where: ? v out = peak to peak output voltage ripple i pk - pk = peak to peak inductor ripple current the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: ? v out = . . (i pp ?r esr ) 2 + { i pp ? (1-d) } 2 c out ? f s where: fs = switching frequency d = duty cycle c out = o utput c apacitance v alue input capacitor selection the input capacitor should be selected for ripple current rating, capacitance and voltage rating. the input capacitor must meet the ripple current requirement imposed by the switching current. in continuous conduction mode, the source current of the high-side mosfet is approximately a square wave of duty cycle v out /v in . most of this current is supplied by the input bypass capacitors. the rms value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: . i cin ( rms ) = i out ( max ) * d * (-d) schottky diode selection when paralleled with the bottom mosfet, an optional schottky diode can improve effciency and reduce noise. without this schottky diode, the body diode of the bot - tom mosfet conducts the current during the non-overlap time when both mosfets are turned off. unfortunately, the body di - ode has high forward voltage and reverse recovery problems. the reverse recovery of the body diode causes additional switching noise when the diode turns off. the schottky diode alleviates these sources of noise and additionally improves effciency thanks to its application information
3 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation low forward voltage. the reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. the power dissipation of the schottky diode is determined by: p diode = 2 ? v f ? i out ? t nol ? f s where: t nol = non-overlap time between gh and gl. vf = forward voltage of the schottky diode. loop compensation design the open loop gain of the whole system can be divided into the gain of the error ampli - fer, pwm modulator, buck converter output stage, and feedback resistor divider. in or - der to cross over at the selected frequency fco , the gain of the error amplifer must compensate for the attenuation caused by the rest of the loop at this frequency. the goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. the frst step of compensation design is to pick the loop crossover frequency. high crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. crossover frequency should be higher than the esr zero but less than 1/5 of the switching frequency. the esr zero is contributed by the esr associated with the output capacitors and can be determined by: ? z ( esr ) = 2 ? c out ? r esr the next step is to calculate the complex conjugate poles contributed by the lc out - put flter, ? p(lc) = . . 2 ? l ? c out when the output capacitors are of a ceramic type, the sp6138 evaluation board requires a type iii compensation circuit to give a phase boost of 180 in order to counteract the effects of an under damped resonance of the output flter at the double pole frequency. application information (srz2cz2+1)(sr1cz3+1) (sr esr c ou t + 1) [s^2lc out +s(r esr +r dc ) c out +1] v in sr1cz2(srz3cz3+1)(srz2cp1+1) v ramp_pp v ou t (v olts) + _ v ref (v olts) notes: r esr = output capacitor equivalent series resistance. r dc = output inductor dc resistance. v ramp_pp = sp6132 internal ram p amplitude peak to peak v oltage. condition: cz2 >> cp1 & r1 >> rz3 output load resistance >> r esr & r dc r 2 v ref (r 1 + r 2 ) or v ou t v fbk (v olts) t ype iii v oltage loop compensation g amp (s) gain block pwm stage g pw m gain block output stage g out (s) gain block v oltage feedback g fbk gain block figure 5: sp6138 voltage mode control loop with loop dynamic defnitions: r e sr = output capacitor equivalent series resistance r dc = output inductor dc resistance v ramp _ pp = sp6 38 internal ramp amplitude peak to peak voltage
4 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation application information frequency (hz) error amplifier gain bandwidth product condition: c22 >> cp1, r1 >> rz3 20 log (rz2/r1) gain (db) 1/6.28(r22) (cz2) 1/6.28 (r1) (cz3) 1/6.28 (r1) (cz2) 1/6.28 (rz2) (cp1) 1/6.28 (rz3) (cz3) figure 6: bode plot of type iii error amplifer compensation table 1. input and output stage components selection charts manufacturer series r isat size inductor type website mohms (a) lxw(mm) ht.(mm) cooper dr73-2r2 2.2 16.50 5.5 7.6x6.0 3.6 shielded ferrite core www.cooperet.com manufacturer esr ripple current size voltage capacitor website mohms (max) ( a ) @ 5 o c rise lxw(mm) ht.(mm) (v) type avx 08053d475mat 4.7 5 1.70 2.01x1.25 1.25 25.0 x5r ceramic www.avx.com avx 08056d226mat 22 5 2.60 2.01x1.25 1.25 6.3 x5r ceramic www.avx.com manufacturer rds(on) id current qg voltage foot print website m (max) (a) nc (typ) nc (max) (v) vishay si7214dn n-channel 47 5.9 4.2 6.5 30 powerpak 1212-8 www.vishay.com note: com p onents hi g hli g hted in bold are those used on the sp6138 evaluation board. inductors - surface mount capacitors - surface mount mosfets - surface mount manufacturer/part no. inductance (uh) manufacturer/part no. capacitance (uf) inductor s p ecification capacitor specification mosfet specification manufacturer/part no. mosfet note: loop compensation component calculations discussed in this datasheet can be quickly iterated with the type iii loop compensation calculator on the web at: www.sipex.com/fles/application-notes/typeiiicalculator.xl s
5 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation application information sp6138 efficiency versus load current @ v in=12v , v out=3.3v 70 75 80 85 90 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) sp6138 load regulation @ v in=12v 3.330 3.335 3.340 3.345 0.5 1.0 1.5 2.0 2.5 3.0 load current (a)
6 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation p ackage: 16 pin qfn
7 oct 24-06 rev j sp6 38 synchronous buck controller ? 2006 sipex corporation ordering information available in lead free packaging. to order add "-l" suffx to part number. example: sp6138er1/tr = standard; sp6138er1-l/tr = lead free /tr = tape and reel pack quantity is 2500 for qfn. part number temperature range package sp638er ........................................... ... .-40 c to +85 c .......................................... 6 pin qfn sp638er/tr ..................................... ... .-40 c to +85 c ........................................... 6 pin qfn sipex corporation headquarters and sales offce 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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